1. Field of the Invention
The present invention relates to microelectronic device fabrication. In particular, the present invention relates to under bump metallization layers which allow for the use for pure tin or high tin content flip-chip bumps.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. A result of such high density and high functionality in microelectronic devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the microelectronic die in order to connect the microelectronic die to other components, such as an interposer.
The connection mechanism for such high density connection is generally ball grid arrays (BGAs), because the size of the balls or bumps of the array can be made smaller to provide a higher density thereof, and thereby creating a greater number of connections from microelectronic die. BGAs are formed by placing an amount of solder on a microelectronic die pad and heating the solder to a melting point. The surface tension associated with the liquid solder causes the solder to form a solder ball. The solder ball retains its shape as it cools to form a solid solder ball or bump.
As shown in FIG. 8, an exemplary microelectronic package includes a microelectronic die 402 that is mounted on a substrate 404, such as an interposer, a motherboard, and the like, which functionally connects the microelectronic die 402 through a hierarchy of electrically conductive paths (not shown) to the other electronic components (not shown). The illustrated method for electronically mounting the microelectronic die 402 to the substrate 404 is called flip chip bonding. In this mounting method, electrically conductive terminals or pads 406 on an active surface 408 of the microelectronic die 402 are attached directly to corresponding lands 412 on a surface 414 of the substrate 404 using solder bumps or balls 416, which are reflowed to from the attachment therebetween.
The material most commonly used to form solder bumps is lead/tin alloy. However, governments are requiring that the solder used to form the bumps be lead-free, as lead is, of course, known to be toxic to humans. Thus, there has been a move to remove lead from bump fabrication. Currently, substantially pure tin or high tin content alloys (90% or more tin), such as tin/bismuth, eutectic tin/sivler, ternary tin/silver/copper, eutectic tin/copper, and the like, are the most suitable material for lead-free solder bumps. The substantially pure tin or high tin content alloys are formed on an under bump metallization (UMB) (not shown) which is deposited on the microelectronic die pads 406. The UBM provides a reliable electrical and mechanical interface between the microelectronic die pads 406 and the solder bumps 416. A typical UMB for a copper-containing microelectronic die pad and a lead/tin solder ball comprises three layers: an adhesion layer for attachment to the microelectronic pad, a barrier layer over the adhesion layer to prevent contamination between the solder ball and microelectronic die, and a wetting layer between the barrier layer and the solder bump to “wet” or adhere to the solder bump material. The adhesion layer may include titanium, nickel vanadium alloy, and the like. The barrier layer may include chromium, titanium nitride, and the like. The wetting layer is usually nickel, copper, cobalt, gold, or alloys thereof.
However, the use of pure tin or high tin content alloys is problematic because tin reacts readily with under-bump metallization stacks that are commonly used in lead/tin bump processes and excessive reaction leads to bump-to-substrate delamination and/or attacks the underlying copper structures (pads and traces) during reflow, as will be understood to those skilled in the art.
The current method for solving the tin-to-under bump metallization reaction problem is to make the wetting layer very thick (e.g., >5 μm thick nickel wetting layer), such that not all of the wetting layer is consumed during the subsequent thermal stresses that the microelectronic package must endure during manufacture and while in service. However, this method is not compatible with the mechanically fragile low dielectric constant (low-k) interlayer dielectric (ILD) materials (i.e., dielectric materials with a dielectric constant below silicon dioxide), because the package-induced stresses are transferred into the hard, thick nickel material at the base of the bump and are subsequently directed into the microelectronic die. The stresses then cause low k ILD cohesive failure and/or low k ILD-to-etchstop adhesive failure.
This incompatibility with low-k ILD materials is a significant problem because, as integrated circuits have become smaller and smaller, it has become necessary to use low-k ILD materials in the fabrication thereof in order to obtain low capacitance between the interconnects. Decreasing this capacitance between the interconnects results in several advantages, including reduced RC delay, reduced power dissipation, and reduced cross-talk between the interconnects.
Therefore, it would be advantageous to develop apparatus and techniques to form an under bump metallization structure that prevents tin contamination which does not translate significant stress into structure abutting the under bump metallization.